1. Field of the Invention
The present invention relates to a Silicon-On-Insulator (SOI) device, and more particularly to a SOI device capable of removing a floating body effect and improving a static electricity characteristic and a method of fabricating the same.
2. Description of the Related Art
It is well known that a n-channel MOSFET comprises a p-type body, a n-type gate, and n-type source/drain regions. A p-channel MOSFET comprises a n-type body, a p-type gate, and p-type source/drain regions.
The p-channel and n-channel MOSFETS with such structures have generally been integrated in a single crystal silicon (Si) wafer comprised of bulk Si to form CMOS devices. Recently, progress has been made on a development of a technique for integrating the MOSFETS in a SOI wafer with a stack structure of a base substrate, a buried oxide layer, and a semiconductor layer.
A MOSFET integrated in a SOI wafer, i.e., a SOI device, has the advantages of high speed due to low junction capacitance, low voltage driving due to low threshold voltage, and decreased latch-up due to complete isolation, as compared with a device integrated in a single crystal Si wafer.
The MOSFET integrated in the single crystal Si wafer is easily connected to fixed potentials. Unlike MOSFET devices constructed on the single crystal Si wafer, however, the MOSFET devices integrated in the SOI wafer can experience a floating body effect, such as a kink effect and a parasitic vertical type bipolar operation because its body is not connected to fixed potential and may float from ground. Further, since the electrostatic discharge (hereinafter, xe2x80x9cESDxe2x80x9d) characteristic is poor, the SOI MOSFET does not tend to operate normally.
When the drain voltage is high in a n-channel MOSFET integrated in a SOI wafer, electrons injected into the channel create an electron-hole pair near the drain, due to impact ionization. Because the created hole moves toward a source, and because the source does not contact a substrate to which a ground is applied, excess holes accumulate in a body part of the substrate, which floats, thereby increasing the potential shift. As a result, the threshold voltage of the transistor is lowered, and a kink effect, characterized by increasing drain current, is generated. Therefore, the n-channel MOSFET integrated in the SOI wafer does not operate normally.
When a lot of holes are generated due to the impact ionization, a bias applied to the body is increased, thereby applying a forward bias to the p-n junction between the source region and the body. Consequently, a source carrier flowing into the body turns on a parasitic NPN bipolar transistor comprising the source region, the body region, and the drain region. This generates a parasitic bell-type bipolar operation this is difficult to control by applying current to the MOSFET gate. As a result, the n-channel MOSFET integrated in the SOI wafer does not operate normally.
Moreover, due to the structural and electrical characteristics of the MOSFET integrated in the SOI wafer, static electricity discharged into such a device is not easily dissipated. ESD discharges, therefore, tend to damage the MOSFET, thereby degrading the device performance.
The problem generated by floating the body of the transistor is conventionally solved by forming a back-gate, forming a body contact structure, and/or forming a device on a complete depletion layer.
FIG. 1 is a cross-sectional view showing a SOI device using a conventional back-gate. As shown, a n-channel MOSFET and a p-channel MOSFET are formed on a semiconductor layer 5 of a SOI wafer having a stack structure of a base substrate 1, a buried oxide layer 2, and the semiconductor layer 5. A p+ well 3 and a n+ well 4 for a back-gate are formed on the base substrate 1.
In such a SOI device, bias voltages Vbn and Vbp are respectively applied to the p+ well 3 and the n+ well 4 on the back gate formed on the base substrate, respectively to controlling the threshold voltages of the n-channel and the p-channel MOSFETS.
The characteristics of the SOI device using the back-gate are very sensitive to changes or variations in the structure of the back-gate and the method used to fabricate the substrate terminal, the alignment and the resistance of a contacts to which a bias voltage is applied. Consequently, the design and fabrication processes are difficult to control and stabilize.
FIGS. 2A and 2B are plane views showing a body contact SOI device. FIG. 2A shows body contacts 14a-c which are formed at the end of a channel of an n-channel MOSFET 10 comprising an H type gate 11, an n+ type source region 12 and a drain region 13. A charge accumulated on the body is emitted through the body contacts 14a-c, to thereby reduce the floating body effects.
In FIG. 2B, a n-channel MOSFET 20 is shown which comprises a gate 21, a p+ type source region 22, and an n+ type drain region 23. A body contact 24 is connected to a p+ region 25, which is formed on the source region 22, and which contacts with a body of the lower portion of the channel. The n-channel MOSFET 20 having such structure can restrain the floating body effect with a relatively simple structure as compared with the structure of the n-channel MOSFET 10 in FIG. 2A.
The SOI device shown in FIG. 2A has larger area than an equivalent device formed in the single crystal Si wafer. Particularly, in cases where the width of the device region is large, a hole can not easily reach the body contact as a result of the increased resistance of the channel region. Consequently, a kink effect cannot be effectively suppressed.
In addition, in the SOI device shown in FIG. 2B, the source region 22 and the drain region 23 have symmetrical structures, the source region 22 and the drain region 23 are not switched onto each other when the SOI device is operational.
A method of forming a device on a complete depletion layer has a shortcoming that the thickness of the semiconductor layer in the SOI wafer is defined, since the thickness of the semiconductor layer on which the device will be formed, is maintained to less than of a predetermined thickness.
When static electricity current is emitted to one place, heat is generated in the inner circuit due to the concentrated static electricity current, thereby tending to damage the device. Unlike the general bulk Si device in which the static electricity current and the generated heat are easily dissipated through a well, in SOI device in which the source region and the drain regions are in contact with the buried oxide layer, such a dissipation path does not exist. In an effort to solve the poor static electricity characteristics of the SOI device, a peripheral circuit which prevents static electricity from discharging current to a ground well or the source region is used, thereby protecting the inner circuit from the discharge and the resulting damage.
It is an object of the present invention to provide a SOI device capable of restraining the generation of floating body effects and a method of fabricating the same.
It is another object of the present invention to provide a SOI device capable of improved ESD characteristics and a method of fabricating the same.
To accomplish the aforementioned objects, a SOI device of the present invention, comprising: a base substrate; a buried oxide layer formed on the base substrate but exposing predetermined regions of the base substrate; a body contact layer having the same thickness as the buried oxide layer on the exposed base substrate region; a body layer of a transistor formed on the buried oxide layer and the body contact layer; a gate having a gate oxide layer formed on the body layer; and a drain region and a source region formed in a depth contacting with the buried oxide layer in the body layer region at both sides of the gate, the source region also being in contact with the body contact layer.
A method of fabricating the SOI device of the present invention, comprising: forming a buried oxide layer on a base substrate; etching a predetermined portion of the buried oxide layer to expose the base substrate; forming a body contact layer having the same thickness as the buried oxide layer on the exposed base substrate region; forming a semiconductor layer on the buried oxide layer and the body contact layer; forming a body layer of a transistor contacting with the body contact layer by etching the semiconductor layer; forming a gate electrode having a gate oxide layer on the body layer; and forming a drain region and a source region in a depth contacting with the buried oxide layer in the body layer region at both sides of the gate electrode, the source region also being in contact with the body layer.